ADN4670BCPZ

ADN4670 is a low voltage differential signalling (LVDS) clock driver that expands a differential clock input signal to 10 differential clock outputs. The device is programmable using a simple serial interface, so that one of two clock inputs can be selected (CLK0/CLK0 or CLK1/CLK1 (active high)) and any of the differential outputs (Q0/Q0 to Q9/Q9) can be enabled or disabled (tristated). The ADN4670 is designed for use in 50 ohm transmission line environments. When the enable input EN is high, the device may be programmed by clocking 11 data bits into the shift register. Application includes clock distribution networks.

• Low output skew is <lt/>30 ps (typical)
• Distributes one differential clock input to 10LVDS clock outputs
• Signalling rate up to 1.1 GHz (typical)
• 2.375V to 2.625V power supply range
• ±100mV differential input threshold, input common-mode range from rail-to-rail
• I/O pins fail-safe during power-down: VDD = 0V
• Differential input voltage is 200mV (min, VDD = 2.375V to 2.625V)
• Differential output voltage is 450mV (typ, RL = 100 ohm)
• 32 lead LFCSP-WQ package, operating temperature range from -40°C to +85°C

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