74HCT573PW,118

74HCT573PW,118 is an 8bit D-type transparent latch with 3-state outputs. This device features latch enable (LE) and output enable (active-low OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on active-low OE causes the outputs to assume a high-impedance OFF-state. Operation of the active-low OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. It features ESD protection (HBM JESD22-A114F exceeds 2000V, MM JESD22-A115-A exceeds 200V).

• Wide supply voltage range from 4.5V to 5.5V
• CMOS low power dissipation, high noise immunity
• TTL input level, common 3-state output enable input
• Propagation delay is 20ns typical at (VCC = 4.5V, 25°C)
• Useful as input or output port for microprocessors and microcomputers
• 3-state non-inverting outputs for bus-oriented applications
• Latch-up performance exceeds 100mA per JESD 78 Class II Level B
• Complies with JEDEC standards: JESD8C (2.7V to 3.6V), JESD7A (2.0V to 6.0V)
• Supply current is 8μA maximum at (VI = VCC or GND; IO = 0A; VCC = 5.5V, +25°C)
• Operating temperature range from -40°C to +125°C, TSSOP20 package